1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a static random access memory device using two DRAM cells as one memory cell.
2. Discussion of Related Art
FIG. 1 shows a uni-DRAM cell structure. In FIG. 1, two of the DRAM cells (MC1, MC2) or memory cells are illustrated. Each of the DRAM cells includes one cell transistor TR and one cell capacitor C. In a DRAM cell MC1, a gate of the cell transistor is coupled to a wordline WL1, and a current path of the cell transistor is formed between a bitline BL and one electrode of the cell capacitor. The other electrode of the cell transistor is coupled to a voltage Vp. In a DRAM cell MC2, a gate of the cell transistor is coupled to a wordline WL2, and a current path of the cell transistor is formed between a bitline BLB and one electrode of the cell capacitor. The other electrode of the cell capacitor is coupled to the voltage. The bitlines (BL, BLB) are coupled to a sense amplifier 12.
In the DRAM cell structure of FIG. 1, when the wordline WL1 is selected, cell data stored in the cell capacitor of the DRAM cell MC1 is transferred to the bitline BL by means of charge sharing. Typically, the bitlines (BL, BLB) are precharged to half a power supply voltage for an array (AIVC), i.e., AIVC/2, prior to a sensing operation. A potential of the bitline BL is increased or decreased by the charge sharing. When data of xe2x80x9c1xe2x80x9d is stored in the memory cell MC1, the potential of the bitline is increased by the charge sharing. When data of xe2x80x9c0xe2x80x9d is stored in the memory cell MC1, the potential of the bitline is decreased by the charge sharing. In this case, the sense amplifier 12 senses and amplifies a potential difference between the bitlines (BL, BLB).
It is well known in the art that since cell data may be damaged by leakage current resulting from the characteristic of the DRAM cell structure, electric charges stored in a cell capacitor may be reduced. For this reason, a potential difference between the bitlines is reduced such that it is impossible to carry out a normal sensing operation, and a refresh fail occurs. Thus, the DRAM cell structure requires a refresh operation for maintaining stored data. A refresh cycle of a DRAM cell comprising one cell capacitor and one cell transistor is determined on the basis of a refresh time (tREF) of cell data xe2x80x9c1xe2x80x9d. Here the xe2x80x9crefresh timexe2x80x9d means the maximum time that data stored in a memory cell can be maintained.
One way to realize a reduced power consumption in a semiconductor memory device adopting a DRAM cell structure is to prolong a refresh time or cycle. The refresh time or cycle may be extended by adopting a twin cell structure. A twin cell structure well known in the art is illustrated in FIG. 2.
Referring to FIG. 2, a twin cell includes two DRAM cells (MC1, MC2) each having one cell transistor and one cell capacitor. In the DRAM cell MC1, a gate of the cell transistor is coupled to a wordline WL1. A current path of the cell transistor is formed between a bitline BL and one electrode of the cell capacitor. The other electrode of the capacitor is coupled to a voltage Vp. In the DRAM cell MC2, a gate of the cell transistor is coupled to the wordline WL1. A current path of the cell transistor is formed between a bitline BLB and one electrode of the cell capacitor. The other electrode of the capacitor is coupled to the voltage Vp. The bitlines (BL, BLB) are coupled to a sense amplifier 22. DRAM cells constituting the twin cell store complementary data. For example, when the DRAM cell MC1 stores cell data xe2x80x9c1xe2x80x9d, the DRAM cell MC2 stores cell data xe2x80x9c0xe2x80x9d. On the other hand, when the DRAM cell MC1 stores cell data xe2x80x9c0xe2x80x9d, the DRAM cell MC2 stores cell data xe2x80x9c1xe2x80x9d.
Referring to FIG. 3 showing another twin cell structure, each of DRAM cells (MC1-MC4) has one cell transistor and one cell capacitor. In the DRAM cell MC1, a gate of the cell transistor is coupled to a wordline WL1. A current path of the cell transistor is formed between a bitline BL1 and one electrode of the cell capacitor. In the DRAM cell MC2, a gate of the cell transistor is coupled to the wordline WL1. A current path of the cell transistor is formed between a bitline BL3 and one electrode of the cell capacitor. The bitlines (BL1, BL3) are coupled to a sense amplifier 32. The DRAM cells (MC1, MC2) constitute a twin cell. In the DRAM cell MC3, a gate of the cell transistor is coupled to a wordline WL2. A current path of the cell transistor is formed between the bitline BL2 and one electrode of the cell capacitor. In the DRAM cell MC4, a gate of the cell transistor is coupled to the wordline WL2. A current path of the cell transistor is formed between the bitline BL4 and one electrode of the cell capacitor. The bitline (BL2, BL4) are coupled to a sense amplifier 34. The DRAM cells (MC3, MC4) constitute a twin cell. DRAM cells each constituting a twin cell store complementary data. Thus, a semiconductor memory device adopting the twin cell structure has a longer refresh cycle or time than a semiconductor memory device adopting a uni-cell structure. This is explained in detail below.
FIG. 4 is a circuit diagram showing a conventional sense amplifier, and FIG. 5 is a timing diagram for explaining a read operation of an SRAM device having a twin cell structure. The read operation of the SRAM device is now described with reference to FIG. 2, FIG. 4, and FIG. 5. Prior to activation of a wordline WL1, bitlines BL and BLB are precharged to a precharge voltage VBL, i.e., AIVC/2, through a bitline precharge unit 30. It is assumed that cell data xe2x80x9c1xe2x80x9d is stored in a DRAM cell MC1 and cell data xe2x80x9c0xe2x80x9d is stored in a DRAM cell MC2. Under this assumption, a node CN1, i.e., a connection node of a cell capacitor and a transistor, of the DRAM cell MC1 has a power supply voltage (AIVC) corresponding to the cell data xe2x80x9c1xe2x80x9d, and a cell node CN2 of the DRAM cell MC2 has a ground voltage GND corresponding to the cell data xe2x80x9c0xe2x80x9d. As the wordline WL1 is activated, charge sharing is established between the bitline BL and a cell capacitor of the DRAM cell MC1 as well as between the bitline BLB and a cell capacitor of the DRAM cell MC2. From the charge sharing, a voltage of the bitline BL is increased by voltage VCS (meaning a voltage gained by subtracting a precharge voltage VBL from a charge-shared bitline voltage) and a voltage of the bitline BLB is decreased by the voltage VCS, as shown in FIG. 5.
Following the charge sharing operation, when a voltage difference between the bitlines (BL, BLB) is sufficiently amplified, a column selection line CSL is activated, as shown in FIG. 5. As the column selection line is activated, input/output lines and the bitlines are electrically connected to each other. Since an input/output line having a high loading capacitance is precharged to internal power supply voltage IVC, voltages of the bitline BLB and the cell node CN1, which drop toward the ground voltage, are clamped to a specific voltage level. In this case, the voltages of the bitline and the cell node are scarcely affected by the activation of the column selection line. Following inactivation of the column selection line, voltages of the bitline BLB and the cell node CN2 drop to the ground voltage. If the cell data xe2x80x9c1xe2x80x9d and the cell data xe2x80x9c0xe2x80x9d are re-stored in the cell nodes (CN1, CN2) according to the voltages of the bitlines (BL, BLB), the wordline WL1 is inactivated and the bitlines are precharged to the precharge voltage VBL.
As described above, since DRAM cells each constituting a twin cell store complementary data, a double voltage difference is made between bitlines as compared to a uni-cell structure. As shown in FIG. 5, the bitline BL coupled to the DRAM cell MC1 storing the cell data xe2x80x9c1xe2x80x9d is increased by VCS by way of the charge sharing, while the bitline BLB coupled to the DRAM cell MC2 storing the cell data xe2x80x9c0xe2x80x9d is decreased by VCS by way of the charge sharing. From the standpoint of the sense amplifier 12, the voltage difference between the bitlines (BL, BLB) is 2VCS. Therefore, in a twin cell structure, the criterion to decide a refresh cycle or time is not needed. Further, a normal sensing operation may be performed even if a potential of a cell node of a DRAM cell storing the cell data xe2x80x9c1xe2x80x9d becomes lower than a bitline precharge voltage by leakage current. This leads to rapid increase in refresh time or cycle of a semiconductor memory device adopting the twin cell structure. For example, the twin cell structure has the refresh cycle or time (tREF) of several seconds, while the uni-cell structure has the refresh time of 100-200 ms. For this reason, stand-by current of the memory device adopting the twin cell structure can be remarkably reduced.
Although representative semiconductor memory devices adopting a twin cell structure are DRAM devices, static random access memory devices (hereinafter referred to as xe2x80x9cSRAMxe2x80x9d devices) can be realized by adopting the same. An SRAM device adopting the twin cell structure is disclosed in the data sheet of product number xe2x80x9cK1S321615Mxe2x80x9d (May, 2001) of Samsung Electronics Co., Ltd., entitled xe2x80x9c2Mxc3x9716 bit Uni-Transistor Random Access Memoryxe2x80x9d, which is a so-called xe2x80x9cUtRAMxe2x80x9d. The SRAM devices adopting the twin cell structure are constructed internally in the same way as the DRAM devices. Meanwhile, an externally supplied command is identical with that of the SRAM device. Unlike a DRAM device adopting the twin cell structure, the SRAM device adopting the twin cell structure has no special external command for a refresh operation. Typically, the refresh operation of the SRAM device adopting the twin cell structure is automatically carried out through control means constructed therein without an external refresh command. As is well known in the art, the refresh operation is substantially identical with the read operation except that sensed data is not outputted to an exterior.
In the case of the SRAM device adopting the twin cell structure, since a refresh operation is carried out without an external refresh command, the refresh operation of at least one clock cycle is needed even though a read/write command is inputted. This may result in loss or damage of stored data. Consequently, access time or speed of the SRAM device adopting the twin cell structure becomes comparatively slow. Therefore, in the case of the SRAM device adopting the twin cell structure, there is a need for a novel control method to enhance the access time or access speed.
The present invention is directed to an SRAM device having a DRAM cell structure and to a method of controlling operations of a static random access memory device, capable of reducing a chip size.
According to an embodiment of the present invention, a first bitline coupled to a first cell transistor and a second bitline coupled to a second cell transistor are charged to a first voltage. After activating a wordline commonly coupled to the first and second cell transistors, a difference between voltage on the first bitline and voltage on the second bitline is sensed and amplified. Finally, when the voltage on one of the first and second bitlines is equivalent to a second voltage lower than the first voltage, an activated wordline is inactivated. The first voltage is a power supply voltage for an array, and the second voltage is a ground voltage. A charge operation is carried out before or after a read, write or refresh operation.
According to an embodiment of the present invention, a static random access memory device comprises a plurality of twin cells, a row selection circuit, a bitline precharge circuit, and a sense amplifier circuit. The twin cells are arranged in a matrix of rows and columns. Each of the twin cells has a first memory cell and a second memory cell. The row selection circuit activates one of the rows in response to a row address, and inactivates an activated row until voltage on one of the first and second bitline reaches a ground voltage. The bitline precharge circuit charges first and second bitlines of each of the columns to a power supply voltage in response to a precharge control signal. The sense amplifier circuit senses and amplifies a voltage difference between the first and second bitlines of each column.
In this embodiment, the first bitline is coupled to a first cell capacitor through a first cell transistor. The second bitline is coupled to a second cell capacitor through the second cell transistor. The first cell transistor and the first capacitor constitute a first memory cell. The second cell transistor and the second cell capacitor constitute a second memory cell. The first and second memory cells constitute a twin cell.
In this embodiment, the sense amplifier circuit is coupled to the first bitline, the second bitline, the power supply voltage, and a signal line. The signal line is driven by a line driver to have one of the power supply voltage and the ground voltage.
In this embodiment, the power supply voltage is used for an array that includes the twin cells.